View ML2036CP_135686.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

March 1997
ML2036* Serial Input Programmable Sine Wave Generator with Digital Gain Control
GENERAL DESCRIPTION
The ML2036 is a monolithic sine wave generator whose output is programmable from DC to 50kHz. No external components are required. The frequency of the sinewave output is derived from either an external crystal or clock input, providing a stable and accurate frequency reference. The frequency is programmed by a 16-bit serial data word. The ML2036 provides for a VOUT amplitude of either VREF or VREF/2. Also included with the ML2036 is an inhibit function which allows the sinewave output to be held at zero volts after completing the last half cycle of the sine wave in progress. Two digital clock outputs are provided to drive other devices with one half or one eighth of the input clock frequency. The ML2036 is intended for telecommunications and modem applications that need low cost and accurate generation of precise test tones, call progress tones, and signaling tones.
FEATURES
s s s
Programmable output frequency - DC to 50kHz Low gain error and total harmonic distortion 3-wire SPI compatible serial microprocessor interface with double buffered data latch Fully integrated solution - no external components required Frequency resolution of 1.5Hz (0.75Hz) with a 12MHz clock input Onboard 3 to 12MHz crystal oscillator Clock outputs of 1/2 or 1/8 of the input clock frequency Synchronous or asynchronous data loading capability Compatible with ML2031 and ML2032 tone detectors and ML2004 logarithmic gain/attenuator
s
s
s s s s
BLOCK DIAGRAM (Pin Configuration Shown for 14-Pin PDIP Version)
9 13
VREF
GAIN
5k
5k
CLK IN
14
CRYSTAL OSCILLATOR /2
8-BIT DAC 8 PHASE ACCUMULATOR & 512 POINT SINE LOOK-UP TABLE 16
SMOOTHING FILTER
+
VOUT
10
CLK OUT 1
3
VCC
8
/2 CLK OUT 2
4
/2
ZERO DETECT
AGND
11
LATI
4
16-BIT DATA LATCH 16 16-BIT SHIFT REGISTER
DGND
12
SCK
2
SID
3
VSS
1
PDN-INH
2
* Some Packages Are Obsolete
1
ML2036
PIN CONFIGURATION
ML2036 14-Pin PDIP (P14)
VSS 1 PDN-INH 2 CLK OUT 1 3 CLK OUT 2 4 SCK 5 SID 6 LATI 7 14 CLK IN 13 GAIN 12 DGND 11 AGND 10 VOUT 9 8 VREF VCC NC VSS PDN-INH CLK OUT 1 CLK OUT 2 SCK SID LATI
ML2036 16-Pin Wide SOIC (S16W)
1 2 3 4 5 6 7 8 TOP VIEW 16 15 14 13 12 11 10 9 CLK IN GAIN NC DGND AGND VOUT VREF VCC
TOP VIEW
PIN DESCRIPTION (Pin Number in Parentheses is for SOIC Version)
PIN NAME FUNCTION PIN NAME FUNCTION
1 (2) 2 (3)
VSS PDN-INH
Negative supply (-5V). Three level input which controls the inhibit and power down modes. Current source pull-up to VCC. Digital clock output from the internal clock generator that can drive other devices at fCLK OUT 1 = fCLK IN/2. Digital clock output from the internal clock generator that can drive other devices at fCLK OUT 2 = fCLK IN/8. Serial clock. Digital input which clocks in serial data on its rising edges. Serial input data which programs the frequency of VOUT. Digital input which latches serial data into the internal data latch on falling edges.
8 (9) 9 (10)
VCC VREF
Positive supply (5V). Reference input. The voltage on this pin determines the peak-topeak swing of VOUT. VREF can be tied to VCC. Analog output. Analog ground. All analog inputs and outputs are referenced to this point. Digital ground. All digital inputs and outputs are referenced to this point. Sets VOUT peak amplitude to VREF or VREF/2. Current source pulldown to DGND. Clock input. The internal clock can be generated by tying a 3 to 12MHz crystal from this pin to DGND, or by applying a digital clock signal directly to the pin.
3 (4)
CLK OUT 1
10 (11) VOUT 11 (12) AGND
4 (5)
CLK OUT 2
12 (13) DGND
5 (6)
SCK
13 (15) GAIN
6 (7) 7 (8)
SID LATI
14 (16) CLK IN
2
ML2036
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC .............................................................................................. 6.5V VSS ............................................................................................. -6.5V VOUT .................................................... VSS - 0.3V to VCC + 0.3V Voltage on any other pin ........ GND - 0.3V to VCC + 0.3V Input Current ........................................................ 25mA Junction Temperature .............................................. 150C Storage Temperature Range ...................... -65C to 150C Lead Temperature (Soldering, 10 sec) ...................... 260C Thermal Resistance (qJA) 14-Pin PDIP ..................................................... 88C/W 16-Pin Wide SOIC .......................................... 105C/W
OPERATING CONDITIONS
Temperature Range ML2036CX ................................................. 0C to 70C ML2036IX ............................................... -40C to 85C VCC Range ................................................... 4.5V to 5.5V VSS Range ................................................. -4.5V to -5.5V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 4.5V to 5.5V, VSS = -4.5V to -5.5V, VREF = 2.5V to VCC, CLK IN = 12.352MHz, CL = 100pF, RL = 1kW, TA = Operating Temperature Range (Note 1)
SYMBOL OUTPUT HD Harmonic Distortion (Note 2) (2nd and 3rd Harmonic) SND Signal to Noise + Distortion (Note 2) 20Hz to 5kHz 5kHz to 50kHz 200Hz to 3.4kHz, fOUT BW = 200Hz to 4kHz 20Hz to 50kHz, fOUT BW = 20 Hz to 150kHz VGN Gain Error (Note 2) 20Hz < fOUT < 5kHz 5kHz < fOUT < 50kHz ICN Idle Channel Noise Power Down Mode, Cmsg Weighted Power Down Mode, 1kHz Inhibit Mode, 1kHz PSRR Power Supply Rejection Ratio 200mVP-P, 0 - 10kHz Sine, Measured on VOUT VOS VP-P VOUT Offset Voltage (Note 3) Peak-to-Peak Output Voltage (Note 2) GAIN = VCC GAIN = DGND VOUT Swing RREF Reference Input Resistance GAIN = VCC VSS + 1.5 1 6 VREF VREF/2 VCC -1.5 VCC VSS -20 50 500 -40 -40
(2.5+VP-P) 100
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
-45 -40 -45 -40 0.15 0.3 0
dB dB dB dB dB dB dBrnc nV/OHz nV/OHz dB dB V V V V MW
OSCILLATOR VIL CLK VIH CLK IIL CLK IIH CLK CIN CLK CLK IN Input Low Voltage CLK IN Input High Voltage CLK IN Input Low Current CLK IN Input High Current CLK IN Input Capacitance 12 3.5 -250 250 1.5 V V A A pF
3
ML2036
ELECTRICAL CHARACTERISTICS
SYMBOL OSCILLATOR (Continued) tCKI CLK IN On/Off Period CLK OUT 1/CLK IN Frequency Ratio CLK OUT 2/CLK IN Frequency Ratio t1R, t2R CLK OUT 1, CLK OUT 2 Rise Time tR = tF = 10ns, 2.5V Midpoint See Figure 2 See Figure 2 CL = 40pF, 10% to 90% CL = 100pF, 0.8V to 2.0V Transition t1F, t2F CLK OUT 1, CLK OUT 2 Fall Time CL = 40pF, 90% to 10% CL = 100pF, 2.0V to 0.8V Transition LOGIC VIL VIH VI1 VI2 VI3 IIL-PDN IIH-GAIN IIL IIH CIN VOL VOH tSCK tDS tDH tLPW tLH tLS SUPPLY ICC VCC Current No Load, VCC = VREF = 5.5V No Load, Power Down Mode ISS VSS Current No Load, VCC = VREF = 5.5V, VSS = -5.5V No Load, Power Down Mode
Note 1: Note 2: Note 3: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Maximum peak-to-peak voltage for the output sine wave is: VOUT(P-P) (125kV x Hz)/fOUT. For example, at 50kHz, the maximum output voltage swing is 2.5V P-P. Offset voltage is a function of the peak-to-peak output voltage. For example, if VOUT(P-P) = 2.5V, VOS = 50mV max.
(Continued)
CONDITIONS MIN TYP MAX UNITS
PARAMETER
30 0.49 0.122 0.51 0.128 20 20 20 20
ns
ns ns ns ns
Input Low Voltage (LATI, SCK, SID, GAIN) Input High Voltage (LATI, SCK, SID, GAIN) Input Low Voltage - PDN-INH Inhibit Stage Voltage - PDN-INH Input High Voltage - PDN-INH PDN-INH Input Low Current GAIN Input High Current Input Low Current (LATI, SCK, SID, GAIN) PDN-INH = 0V GAIN = VCC VIN = 0V 2.0 -70 5 -1 -20 20 2.0 -0.5
0.8
V V
0.8 VSS + 0.5
V V V
-5 70
A A A
Input High Current (LATI, SCK, SID, GAIN) VIN = VCC Input Capacitance Output Low Voltage Output High Voltage Serial Clock On/Off Period SID Data Setup Time SID Data Hold Time LATI Pulse Width LATI Hold Time LATI Setup Time IOL = -2mA IOH = 2mA 4.0 100 50 50 50 50 50 5
1
A pF
0.4
V V ns ns ns ns ns ns
5.5 2 -3.5 -100
mA mA mA A
4
ML2036
tCKI CLK IN tSCK SCK tDS SID tLH tDH tSCK tCKI
tLS LATI tLPW
Figure 1. Serial Interface Timing.
fCLKIN CLKIN fCLK1 CLKOUT1 fCLK2 CLKOUT2 t2F t2R t1R t1F
fCLK PARAMETERS REFERRED TO 1.4V MIDPOINT
Figure 2. Digital Clock Output Timing.
100 75 50
INPUT CURRENT (A)
25 0 -25 -50 -75 -100
0
1
2
3
4
5
INPUT VOLTAGE (V)
Figure 3. CLK IN Input Current vs. Input Voltage.
5
ML2036
SID
16-BIT SHIFT REGISTER (16 BITS) ***
LATI
16-BIT DATA LATCH (16 BITS) *** ***
A16 A0
-
A20 A15
21-BIT ADDER
B0-B20
BINARY PHASE ACCUMULATOR fREF
Q0
-
SUM (21 BITS) *** 21-BIT LATCH *** INPUT TO QUADRANT COMPLEMENTOR
Q20
LEAST SIGNIFICANT (12 BITS)
***
PHASE SAMPLES (7 BITS)
SIGN BIT QUADRANT BIT
CLKIN
CRYSTAL OSCILLATOR
/4
QUADRANT COMPLEMENTER *** (7 BITS) READ-ONLY MEMORY (128 X 7) *** (7 BITS) SIGN COMPLEMENTOR *** (7 BITS) fREF OUTPUT LATCH *** (7BITS) SIGN BIT SIGN BIT SIGN BIT
T= INPUT TO ROM
1 fREF
INPUT TO SIGN COMPLEMENTOR
PICTORIAL PRESENTATION OF DIGITAL DATA
INPUT TO OUTPUT LATCH
INPUT TO D/A CONVERTER
8-BIT DIGITAL-TO-ANALOG CONVERTER
LOW-PASS FILTER
INPUT TO LOW-PASS FILTER (ANALOG SIGNAL) OUTPUT OF LOW-PASS FILTER (ANALOG SIGNAL)
SINEWAVE OUTPUT
Figure 4. Detailed Block Diagram of the ML2036.
6
ML2036
FUNCTIONAL DESCRIPTION
The ML2035 is composed of a programmable frequency generator, a sine wave generator, a crystal oscillator, and a serial digital interface. The ML2036 frequency and sine wave generator functional block diagram is shown in Figure 4. PROGRAMMABLE FREQUENCY GENERATOR The programmable frequency generator produces a digital output whose frequency is determined by a 16-bit digital word. The frequency generator is composed of a phase accumulator which is clocked at fCLK IN/4. The value stored in the data latch is added to the phase accumulator every 4 cycles of CLK IN. The frequency of the analog output is equal to the rate at which the accumulator overflows and is given by the equation: fOUT = fCLKIN x D15 - D0 223 The ML2036 has a VREF input that can be tied to VCC or generated from an external voltage. With the GAIN input equal to a logic "1", the sine wave peak-to-peak voltage is equal to VREF; with the GAIN equal to a logic "0", the peak voltage is VREF/2. However, the overall output voltage swing is limited to no closer than 1.5V to either rail. This means that to avoid clipping, VREF can only be tied to VCC when GAIN is a logic "0". The sinewave output is referenced to AGND. The analog section is designed to operate over a range from DC to 50kHz. Due to slew rate limitations, the peakto-peak output voltage must be limited to VOUT(P-P) (125kV x Hz)/fOUT. For example, an output at 50kHz must be limited to 2.5VP-P. VOUT can drive a 1kW, 100pF load and swing to within 1.5V of VCC and VSS, provided the slew rate limitations mentioned above are not exceeded. The output offset voltage, VOS, is a function of the peak-topeak output voltage and is specified as:
0
5
DEC
(1)
The frequency resolution and the minimum frequency are the same and is given by the following equation:
fMIN = fCLKIN 223
VOS0MAX5 =
. 25 + V 0 5 100
OUT P -P
(3)
For example, if VOUT(P-P) = 2.5V: (2)
When fCLK IN = 12.352MHz, DfMIN = 1.5Hz (0.75Hz). Lower frequencies are obtained by using a lower input clock frequency. Due to the phase quantization nature of the frequency generator, spurious tones can be present in the output range of -55dB relative to fundamental. The energy from these tones is included in the signal to noise + distortion specification. The frequency of these tones can be very close to the fundamental. Therefore, it is not practical to filter them out. SINE WAVE GENERATOR The sine wave generator is composed of a sine look-up table, a DAC, and an output smoothing filter. The sine look-up table is addressed by the phase accumulator. The DAC is driven by the output of the look-up table and generates a staircase representation of a sine wave. The output filter smoothes the analog output by removing the high frequency sampling components. The resultant voltage on VOUT is a sinusoid with the second and third harmonic distortion components at least 45dB below the fundamental.
SCK SID LATI 0 1 2 3 4 5 6 7
VOS0 MAX5 =
. . 25 + 25 = 50mV 100
CRYSTAL OSCILLATOR The crystal oscillator generates an accurate reference clock for the programmable frequency generator. The internal clock can be generated with a crystal or external clock. If a crystal is used, it must be placed between CLK IN and DGND of the ML2036. An on-chip crystal oscillator will then generate the internal clock. No other external capacitors or components are required. The crystal should be a parallel-resonant type with a frequency between 3MHz to 12.4MHz. It should be placed physically as close as possible to the CLK IN and DGND. An external clock can drive CLK IN directly if desired. The frequency of this clock can be anywhere between 0 and 12MHz.
8
9
10
11
12
13
14
15
Figure 5. Serial Interface Timing.
7
ML2036
FUNCTIONAL DESCRIPTION (Continued)
The crystal must have the following characteristics: 1. Parallel resonant type 2. Frequency: 3MHz to 12.4MHz 3. Maximum equivalent series resistance of 15W at a drive levels of 1W to 200W, and 30W at drive levels of 10nW to 1W 4. Typical load capacitance: 18pF 5. Maximum case capacitance: 7pF The frequency of oscillation will be a function of the crystal parameters and PC board capacitance. Crystals that meet these requirements at 12.352000MHz are M-tron 3709-010 12.352 for 0C to 70C and 3709-020 12.352 for -40C to 85C operation. The ML2036 has two clock outputs that can be used to drive other external devices. The CLK OUT 1 output is a buffered output from the oscillator divided by 2. The CLK OUT 2 output is a buffered output from the oscillator divided by 8. SERIAL DIGITAL INTERFACE The digital interface consists of a shift register and data latch. The serial 16-bit data word on SID is clocked into a 16-bit shift register on rising edges of the serial shift clock, SCK. The LSB should be shifted in first and the MSB last as shown in Figure 4. The data that has been shifted into the shift register is loaded into a 16-bit data latch on the falling edge of LATI. To insure that true data is loaded into the data latch from the shift register, LATI falling edge should occur when SCK is low, as shown in figure 1. LATI should be low while shifting data into the shift register to avoid inadvertently entering the power down mode. Note that all data is entered and latched on the edges, not levels, of SCK and LATI. The analog circuits in ML2036 are powered from VCC to VSS and are referenced to AGND. The digital circuits in the device are powered from VCC to DGND. It is recommended that AGND and DGND be connected together close to the device, and have a good connection back to the power source. It is recommended that the power supplies to the device should be bypassed by placing decoupling capacitors from VCC to AGND and VSS to AGND as physically close to the device as possible. INHIBIT AND POWER DOWN MODES The ML2036 has an inhibit mode and a power down mode which are controlled by the three-level PDN-INH input as described in Table 1. If a logic "1", (VI3) is applied to the PDN-INH pin, the power down mode is entered by entering all zeros in the shift register and applying a logic "1" to LATI and holding it high. A zero data detect circuit detects when all bits in the shift register are zeros. In this state, the power consumption is reduced to 11.5mW max, and VOUT goes to 0V as shown in Figure 6 and appears as 10kW to AGND. CLK IN can be left active or removed during power down mode. Also, the ML2036 can be placed in the power down mode by applying a logic "0" to the PDN-INH pin, regardless of the contents of the shift register and the state of LATI. If VSS to VSS + 0.5V (VI2) is applied to the PDN-INH pin, the inhibit mode is entered by shifting all zeros into the shift register and applying a logic "1" to the LATI pin. Once the inhibit mode is entered VOUT will complete the last half cycle of the sinewave and then be held at approximately VOS, such that no voltage step occurs, as shown in Figure 6. POWER SUPPLIES
8
ML2036
PDN-INH MODE PDN(1) Inhibit PDN-INH PIN VI1, Logic "0" VI2, Inhibit State Voltage, VSS to VSS + 0.5V VI3, Logic "1" DATA IN SHIFT REG. X All 0`s
LATI X Logic "1"
SINE WAVE OUTPUT VOUT = 0V (10kW to AGND) VOUT goes to approximately VOS at the next VOS crossing (See Figure 6) VOUT = 0V (10kW to AGND)
PDN(1)
All 0`s
Logic "1"
Note 1:
In the power down mode, the oscillator, CLK OUT 1 and CLK OUT 2, shift register, and data latch are all functional.
Table 1. Three Level PDN-INH Functions.
POWER DOWN MODE 0V
VOS
INHIBIT MODE 0V
VOS
VX
V f |VX| = PEAK , FOR fOUT CLK 256 2048 |VX| VPEAK + V 8 fOUT + PEAK SIN 256 fCLK 512 FOR fOUT > fCLK 2048
SCK SID LATI 0 1 2 3 4 5 6 7 8 9 10 11 12 131415
Figure 6. Power Down and Inhibit Mode Waveforms.
9
ML2036
TYPICAL APPLICATIONS
RECEIVE LINE INTERFACE ML2003 ML2004 ML2008 ML2009 ATTENUATION /GAIN ML2020 ML2021 LINE EQUALIZER
ML2031 ML2032 TONE DETECTOR
P
LOOPBACK RELAY
TRANSMIT LINE INTERFACE
ML2003 ML2004 ML2008 ML2009 ATTENUATION /GAIN
ML2036 TONE GENERATOR
Figure 7. 4-Wire Termination Equipment.
5V ML2036 VCC 0.1F GND 0.1F VSS -5V VREF 2.5V REF VOUT GAIN
Figure 8. Sine Wave Generator with 2.5VP-P.
10
ML2036
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P14 14-Pin PDIP
0.740 - 0.760 (18.79 - 19.31) 14
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.25)
0.070 MIN (1.77 MIN) (4 PLACES)
1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: S16W 16-Pin Wide SOIC
0.400 - 0.414 (10.16 - 10.52) 16
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.009 - 0.013 (0.22 - 0.33)
11
ML2036
ORDERING INFORMATION
PART NUMBER ML2036CP ML2036CS ML2036IP ML2036IS (Obsolete) TEMPERATURE RANGE 0C to 70C 0C to 70C -40C to 85C -40C to 85C PACKAGE 14-Pin PDIP (P14) 16-Pin Wide SOIC (S16W) 14-Pin PDIP (P14) 16-Pin Wide SOIC (S16W)
(c) Micro Linear 1997. is a registered trademark of Micro Linear Corporation. Products described in this document may be covered by one or more of the following patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295
DS2036-01
12

▲Up To Search▲

Price & Availability of ML2036CP

	To Download ML2036CP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .